7.8. Understanding and Troubleshooting Configuration Pin Behavior
Configuration typically fails for one of the following reasons:
- The host times outs
- A configuration data error occurs
- An external event interrupts configuration
- An internal error occurs
Here are some very common causes of configuration failures:
Check OSC_CLK_1 frequency. It must match the frequency you specified in the Intel® Quartus® Prime Software and the clock source on your board.
- Ensure a free running reference clock is present for designs using transceivers, PCIe* , or HBM2. These reference clocks must be available until the device enters user mode.
- For designs using the HPS and the external memory interface (EMIF), ensure that the EMIF clock is present.
- For designs using SmartVID (-V and -E devices), ensure that this feature is set-up and operating correctly. Ensure that the voltage regulator supports SmartVID.
Here are some debugging suggestions that apply to any configuration mode:
- To rule out issues with OSC_CLK_1 select the Internal Oscillator option in the Intel® Quartus® Prime.
- Try configuring the Intel Agilex® 7 device with a simple design that does not contain any IP. If configuration via a non-JTAG scheme fails with a simple design, try JTAG configuration with the MSEL pins set specifically to JTAG.
The following topics describe the expected behavior of configuration pins. In addition, these topics provide some suggestions to assist in debugging configuration failures. Refer to the separate sections on each configuration scheme for debugging suggestions that pertain to a specific configuration scheme.
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