1. Intel Agilex® 7 Configuration User Guide 2. Intel Agilex® 7 Configuration Details 3. Intel Agilex® 7 Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Intel Agilex® 7 Configuration Features 7. Intel Agilex® 7 Debugging Guide 8. Intel Agilex® 7 Configuration User Guide Archives 9. Document Revision History for the Intel Agilex® 7 Configuration User Guide
2.1. Intel Agilex® 7 Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS and Transceivers 2.5. Intel Agilex® 7 Configuration Pins 2.6. Configuration Clocks 2.7. Intel Agilex® 7 Configuration Time Estimation 2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
220.127.116.11.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins 18.104.22.168.2. PFL II IP Recommended Design Constraints for Using QSPI Flash 22.214.171.124.3. PFL II IP Recommended Design Constraints for using CFI Flash 126.96.36.199.4. PFL II IP Recommended Constraints for Other Input Pins 188.8.131.52.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Skew Tolerance Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Intel® Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example 5.7. Debugging Guidelines for RSU Configuration
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist 7.2. Intel Agilex® 7 Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. Configuration File Format Differences 7.5. Understanding SEUs 7.6. Reading the Unique 64-Bit CHIP ID 7.7. E-Tile Transceivers May Fail To Configure 7.8. Understanding and Troubleshooting Configuration Pin Behavior
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
184.108.40.206. Configuration Pointer Block Layout
The configuration pointer block contains a list of application image addresses. The SDM tries the images in sequence until one of them is successful or all fail. The structure contains the following information:
|Offset||Size (in bytes)||Description|
|0x00||4||Magic number 0x57789609|
|0x04||4||Size of pointer block header (0x18 for this document)|
|0x08||4||Size of pointer block (4096 for this document)|
|0x10||4||Offset to image pointers (IPTAB)|
|0x14||4||Total number of image pointer slots allocated = 508|
|0x20 (IPTAB) 16||8||First (lowest priority) image pointer slot (IPTAB)|
|8||Second (2nd lowest priority) image pointer slot|
|8||Last (highest priority) image pointer|
The configuration pointer block can contain up to 508 application image pointers. A typical configuration pointer block update procedure consists of adding a new pointer and potentially clearing an older pointer. Typically, the pointer block update uses one new slot. Consequently, you can make 508 updates before the pointer block must be erased. The erase procedure is called pointer block compression. This procedure is power failure safe, as there are two copies of the pointer block. The copies are in different flash erase sectors. While one copy is being updated the other copy is still valid.
Note: In order to successfully update SPTs and CPBs, the HPS software (U-Boot or Linux) must be configured to support a minimum QSPI erase granularity smaller or equal to CPB and SPT sizes. All supported flash devices offer erase granularities of 4 KB, 32 KB, and 64 KB. HPS software is typically configured with either 4 KB or 64 KB erase granularity. When the HPS software is configured with 64 KB erase granularity, the CPB and SPT sizes must be configured in Programming File Generator to be 64 KB instead of the default 32 KB.
16 The offset may vary in future firmware updates.