Intel Agilex® 7 Configuration User Guide

ID 683673
Date 4/28/2023

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Document Table of Contents Configuration Pointer Block Layout

The configuration pointer block contains a list of application image addresses. The SDM tries the images in sequence until one of them is successful or all fail. The structure contains the following information:

Table 54.  Pointer Block Layout
Offset Size (in bytes) Description
0x00 4 Magic number 0x57789609
0x04 4 Size of pointer block header (0x18 for this document)
0x08 4 Size of pointer block (4096 for this document)
0x0C 4 Reserved
0x10 4 Offset to image pointers (IPTAB)
0x14 4 Total number of image pointer slots allocated = 508
0x18 8 Reserved
0x20 (IPTAB) 16 8 First (lowest priority) image pointer slot (IPTAB)
  8 Second (2nd lowest priority) image pointer slot
  8 Last (highest priority) image pointer
The configuration pointer block can contain up to 508 application image pointers. A typical configuration pointer block update procedure consists of adding a new pointer and potentially clearing an older pointer. Typically, the pointer block update uses one new slot. Consequently, you can make 508 updates before the pointer block must be erased. The erase procedure is called pointer block compression. This procedure is power failure safe, as there are two copies of the pointer block. The copies are in different flash erase sectors. While one copy is being updated the other copy is still valid.
Note: In order to successfully update SPTs and CPBs, the HPS software (U-Boot or Linux) must be configured to support a minimum QSPI erase granularity smaller or equal to CPB and SPT sizes. All supported flash devices offer erase granularities of 4 KB, 32 KB, and 64 KB. HPS software is typically configured with either 4 KB or 64 KB erase granularity. When the HPS software is configured with 64 KB erase granularity, the CPB and SPT sizes must be configured in Programming File Generator to be 64 KB instead of the default 32 KB.
16 The offset may vary in future firmware updates.