Intel Agilex® 7 Configuration User Guide

ID 683673
Date 4/28/2023

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Document Table of Contents Controlling Avalon-ST Configuration with PFL II IP Core

The PFL II IP core in the host determines when to start the configuration process, read the data from the flash memory device, and configure the Intel Agilex® 7 device using the Avalon-ST configuration scheme.
Figure 28. FPGA Configuration with Flash Memory Data

You can use the PFL II IP core to either program the flash memory devices, configure your FPGA, or both. To perform both functions, create separate PFL II functions if any of the following conditions apply to your design:

  • You modify the flash data infrequently.
  • You have JTAG or In-System Programming (ISP) access to the configuration host.
  • You want to program the flash memory device with non-Intel FPGA data, for example initialization storage for an ASSP. You can use the PFL II IP core to program the flash memory device for the following purposes:
    • To write the initialization data
    • To store your design source code to implement the read and initialization control with the host logic