- 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
4. Including the Reset Release Intel® FPGA IP in Your Design
The Reset Release Intel® FPGA IP is available in the Intel® Quartus® Prime Software. This IP consists of a single output signal, nINIT_DONE. The nINIT_DONE signal is the core version of the INIT_DONE pin and has the same function in both FPGA First and HPS First configuration modes. Intel recommends that you hold your design in reset while the nINIT_DONE signal is high or while the INIT_DONE pin is low. When you instantiate the Reset Release IP in your design, the SDM drives the nINIT_DONE signal. Consequently, the IP does not consume any FPGA fabric resources, but does require routing resources.
View the video guide below for a quick walk-through to understand the importance of using Reset Release Intel® FPGA IP and how to include it in your design.
Understanding the Reset Release IP Requirement
Instantiating the Reset Release IP In Your Design
Gating the PLL Reset Signal
Guidance When Using Partial Reconfiguration (PR)
Detailed Description of Device Configuration
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