Arria V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683660
Date 5/12/2017
Document Table of Contents
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1.9. Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device resources.

Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required depends on the configuration.