Arria V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683660
Date 5/12/2017
Document Table of Contents

1.6. Example Designs

Intel provides example designs to familiarize you with the available functionality. Each design connects the device under test (DUT) to an application (APPS) as the figure below illustrates. Certain critical parameters of the APPs component are set to match the values of DUT. If you change these parameters, you must change the APPs component to match. You can change the values for all other parameters of the DUT without editing the APPs component.

Figure 5. Example Design Preset Parameters
  • Targeted Device Family
  • Lanes
  • Lane Rate
  • Application Clock Rate
  • Port type
  • Application Interface
  • Tags supported
  • Maximum payload size
  • Number of functions

The following example designs are available for the Arria V Hard IP for PCI Express. You can download them from the <install_dir>/ ip/altera/altera_pcie/altera_pcie_hip_ast_ec/example_design/<dev> directory:

  • pcie_de_gen1_x2_ast64.qsys
  • pcie_de_gen1_x4_ast64.qsys
  • pcie_de_gen1_x8_ast128.qsys
  • pcie_de_rp_gen1_x4_ast64.qsys
  • pcie_de_rp_gen1_x8_ast128.qsys

Click on the link below to get started with the example design provided in this user guide.