Arria V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683660
Date 5/12/2017
Document Table of Contents

6.1.4. Legacy Interrupts

Legacy interrupts mimic the original PCI level-sensitive interrupts using virtual wire messages. The Arria V hard IP for PCI Express* Endpoint signals a legacy interrupt on the PCIe link using Message TLPs. The term, INTx, refers collectively to the four legacy interrupts, INTA#, INTB#, INTC# and INTD#. The app_int_sts_vec[7:0] input vector controls interrupt generation. The Interrupt Handler Module in the Application Layer asserts app_int_sts[<n>]. In response, the PCI Express* Endpoint generates an Assert_INTx message TLP and sends it upstream. The legacy interrupt handler deasserts app_int_sts[<n>]. In response, the Endpoint generates a Deassert_INTx message TLP and sends it upstream. To use legacy interrupts, you must clear the Interrupt Disable bit, which is bit 10 of the Command register. Then, turn off the MSI Enable bit.

The following figures illustrates interrupt timing for the legacy interface. The legacy interrupt handler asserts app_int_sts_vec[<n>], causing the Hard IP for PCI Express to send a Assert_INTx message TLP. When multi-function operation is enabled, the app_int_sts_vec[7:0] signal controls interrupt generation. For example, asserting app_int_sts_vec[2] generates the Assert_INT[2] TLP message.

Figure 34. Legacy Interrupt Assertion

The following figure illustrates the timing for deassertion of legacy interrupts. The legacy interrupt handler asserts app_int_sts_vec[<n>] causing the Hard IP for PCI Express to send a Deassert_INTx message.

Figure 35. Legacy Interrupt Deassertion