Arria V Avalon-ST Interface for PCIe Solutions: User Guide

Download PDF
ID 683660
Date 5/12/2017
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Arria V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Interrupts 7. Error Handling 8. IP Core Architecture 9. Transaction Layer Protocol (TLP) Details 10. Throughput Optimization 11. Design Implementation 12. Additional Features 13. Hard IP Reconfiguration 14. Transceiver PHY IP Reconfiguration 15. Testbench and Design Example 16. Debugging A. Frequently Asked Questions for PCI Express B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Arria V Avalon-ST Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. Debug Features 1.8. IP Core Verification 1.9. Performance and Resource Utilization 1.10. Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Arria V Hard IP for PCI Express x
2.1. Qsys Design Flow 2.2. Modifying the Example Design 2.3. Using the IP Catalog To Generate Your Arria V Hard IP for PCI Express as a Separate Component
2.1. Qsys Design Flow x
2.1.1. Generating the Testbench 2.1.2. Simulating the Example Design 2.1.3. Generating Synthesis Files 2.1.4. Understanding the Files Generated 2.1.5. Understanding Physical Placement of the PCIe IP Core 2.1.6. Compiling the Design in the Quartus® Prime Software
3. Parameter Settings x
3.1. Avalon-ST System Settings 3.2. Link Capabilities 3.3. Port Function Parameters Shared Across All Port Functions 3.4. Port Function Parameters Defined Separately for All Port Functions
3.3. Port Function Parameters Shared Across All Port Functions x
3.3.1. Device Capabilities 3.3.2. Error Reporting 3.3.3. Link Capabilities 3.3.4. Slot Capabilities 3.3.5. Power Management
3.4. Port Function Parameters Defined Separately for All Port Functions x
3.4.1. Base Address Register (BAR) and Expansion ROM Settings 3.4.2. Base and Limit Registers for Root Ports 3.4.3. Device Identification Registers for Function <n> 3.4.4. Func <n> Device 3.4.5. Func <n> Link 3.4.6. Func <n> MSI and MSI-X Capabilities 3.4.7. Func <n> Legacy Interrupt
4. Interfaces and Signal Descriptions x
4.1. Clock Signals 4.2. Reset, Status, and Link Training Signals 4.3. ECRC Forwarding 4.4. Error Signals 4.5. Interrupts for Endpoints 4.6. Interrupts for Root Ports 4.7. Completion Side Band Signals 4.8. LMI Signals 4.9. Transaction Layer Configuration Space Signals 4.10. Hard IP Reconfiguration Interface 4.11. Power Management Signals 4.12. Physical Layer Interface Signals
4.9. Transaction Layer Configuration Space Signals x
4.9.1. Configuration Space Register Access Timing 4.9.2. Configuration Space Register Access
4.12. Physical Layer Interface Signals x
4.12.1. Serial Data Signals 4.12.2. PIPE Interface Signals 4.12.3. Test Signals
4.12.1. Serial Data Signals x
4.12.1.1. Physical Layout of Hard IP in Arria V Devices 4.12.1.2. Channel Placement in Arria V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. Advanced Error Reporting Capability
5.5. Intel-Defined VSEC Registers x
5.5.1. CvP Registers
5.6. Advanced Error Reporting Capability x
5.6.1. Uncorrectable Internal Error Mask Register 5.6.2. Uncorrectable Internal Error Status Register 5.6.3. Correctable Internal Error Mask Register 5.6.4. Correctable Internal Error Status Register
6. Interrupts x
6.1. Interrupts for Endpoints 6.2. Interrupts for Root Ports
6.1. Interrupts for Endpoints x
6.1.1. MSI and Legacy Interrupts 6.1.2. MSI-X 6.1.3. Implementing MSI-X Interrupts 6.1.4. Legacy Interrupts
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
8. IP Core Architecture x
8.1. Top-Level Interfaces 8.2. Transaction Layer 8.3. Data Link Layer 8.4. Physical Layer 8.5. Multi-Function Support
8.1. Top-Level Interfaces x
8.1.1. Avalon-ST Interface 8.1.2. Clocks and Reset 8.1.3. Local Management Interface (LMI Interface) 8.1.4. Hard IP Reconfiguration 8.1.5. Transceiver Reconfiguration 8.1.6. Interrupts 8.1.7. PIPE
8.2. Transaction Layer x
8.2.1. Configuration Space
9. Transaction Layer Protocol (TLP) Details x
9.1. Supported Message Types 9.2. Transaction Layer Routing Rules 9.3. Receive Buffer Reordering
9.1. Supported Message Types x
9.1.1. INTX Messages 9.1.2. Power Management Messages 9.1.3. Error Signaling Messages 9.1.4. Locked Transaction Message 9.1.5. Slot Power Limit Message 9.1.6. Vendor-Defined Messages 9.1.7. Hot Plug Messages
9.3. Receive Buffer Reordering x
9.3.1. Using Relaxed Ordering
10. Throughput Optimization x
10.1. Throughput of Posted Writes 10.2. Throughput of Non-Posted Reads
11. Design Implementation x
11.1. Making Analog QSF Assignments Using the Assignment Editor 11.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 11.3. Recommended Reset Sequence to Avoid Link Training Issues 11.4. SDC Timing Constraints
12. Additional Features x
12.1. Configuration over Protocol (CvP) 12.2. Autonomous Mode 12.3. ECRC
12.2. Autonomous Mode x
12.2.1. Enabling Autonomous Mode 12.2.2. Enabling CvP Initialization
12.3. ECRC x
12.3.1. ECRC on the RX Path 12.3.2. ECRC on the TX Path
14. Transceiver PHY IP Reconfiguration x
14.1. Connecting the Transceiver Reconfiguration Controller IP Core 14.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
15. Testbench and Design Example x
15.1. Endpoint Testbench 15.2. Root Port Testbench 15.3. Test Driver Module 15.4. Root Port Design Example 15.5. Root Port BFM Overview 15.6. BFM Procedures and Functions 15.7. Setting Up Simulation
15.1. Endpoint Testbench x
15.1.1. Endpoint Testbench for SR-IOV
15.5. Root Port BFM Overview x
15.5.1. BFM Memory Map 15.5.2. Configuration Space Bus and Device Numbering 15.5.3. Configuration of Root Port and Endpoint 15.5.4. Issuing Read and Write Transactions to the Application Layer
15.6. BFM Procedures and Functions x
15.6.1. ebfm_barwr Procedure 15.6.2. ebfm_barwr_imm Procedure 15.6.3. ebfm_barrd_wait Procedure 15.6.4. ebfm_barrd_nowt Procedure 15.6.5. ebfm_cfgwr_imm_wait Procedure 15.6.6. ebfm_cfgwr_imm_nowt Procedure 15.6.7. ebfm_cfgrd_wait Procedure 15.6.8. ebfm_cfgrd_nowt Procedure 15.6.9. BFM Configuration Procedures 15.6.10. BFM Shared Memory Access Procedures 15.6.11. BFM Log and Message Procedures 15.6.12. Verilog HDL Formatting Functions
15.6.9. BFM Configuration Procedures x
15.6.9.1. ebfm_cfg_rp_ep Procedure 15.6.9.2. ebfm_cfg_decode_bar Procedure
15.6.10. BFM Shared Memory Access Procedures x
15.6.10.1. Shared Memory Constants 15.6.10.2. shmem_write Task 15.6.10.3. shmem_read Function 15.6.10.4. shmem_display Verilog HDL Function 15.6.10.5. shmem_fill Procedure 15.6.10.6. shmem_chk_ok Function
15.6.11. BFM Log and Message Procedures x
15.6.11.1. ebfm_display Verilog HDL Function 15.6.11.2. ebfm_log_stop_sim Verilog HDL Function 15.6.11.3. ebfm_log_set_suppressed_msg_mask Task 15.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 15.6.11.5. ebfm_log_open Verilog HDL Function 15.6.11.6. ebfm_log_close Verilog HDL Function
15.6.12. Verilog HDL Formatting Functions x
15.6.12.1. himage1 15.6.12.2. himage2 15.6.12.3. himage4 15.6.12.4. himage8 15.6.12.5. himage16 15.6.12.6. dimage1 15.6.12.7. dimage2 15.6.12.8. dimage3 15.6.12.9. dimage4 15.6.12.10. dimage5 15.6.12.11. dimage6 15.6.12.12. dimage7
15.7. Setting Up Simulation x
15.7.1. Changing Between Serial and PIPE Simulation 15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 15.7.3. Viewing the Important PIPE Interface Signals 15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 15.7.6. Changing between the Hard and Soft Reset Controller
16. Debugging x
16.1. Hardware Bring-Up Issues 16.2. Link Training 16.3. Use Third-Party PCIe Analyzer 16.4. BIOS Enumeration Issues
16.2. Link Training x
16.2.1. Link Hangs in L0 State
C. Document Revision History x
C.1. Document Revision History of the Arria V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History

5.1. Correspondence between Configuration Space Registers and the PCIe Specification

Table 42.  Address Map of Hard IP Configuration Space RegistersFor the Type 0 and Type 1 Configuration Space Headers, the first line of each entry lists Type 0 values and the second line lists Type 1 values when the values differ.

Byte Address

Hard IP Configuration Space Register

Corresponding Section in PCIe Specification

0x000:0x03C

PCI Header Type 0 Configuration Registers

Type 0 Configuration Space Header

0x000:0x03C

PCI Header Type 1 Configuration Registers

Type 1 Configuration Space Header

0x040:0x04C

Reserved

N/A

0x050:0x05C

MSI Capability Structure

MSI Capability Structure

0x068:0x070

MSI-X Capability Structure

MSI-X Capability Structure

0x070:0x074

Reserved

N/A

0x078:0x07C

Power Management Capability Structure

PCI Power Management Capability Structure

0x080:0x0BC

PCI Express Capability Structure

PCI Express Capability Structure

0x0C0:0x0FC

Reserved

N/A

0x100:0x16C

Virtual Channel Capability Structure

Virtual Channel Capability

0x170:0x17C

Reserved

N/A

0x180:0x1FC

Virtual channel arbitration table

VC Arbitration Table

0x200:0x23C

Port VC0 arbitration table

Port Arbitration Table

0x240:0x27C

Port VC1 arbitration table

Port Arbitration Table

0x280:0x2BC

Port VC2 arbitration table

Port Arbitration Table

0x2C0:0x2FC

Port VC3 arbitration table

Port Arbitration Table

0x300:0x33C

Port VC4 arbitration table

Port Arbitration Table

0x340:0x37C

Port VC5 arbitration table

Port Arbitration Table

0x380:0x3BC

Port VC6 arbitration table

Port Arbitration Table

0x3C0:0x3FC

Port VC7 arbitration table

Port Arbitration Table

0x400:0x7FC

Reserved

PCIe spec corresponding section name

0x800:0x834

Advanced Error Reporting AER (optional)

Advanced Error Reporting Capability

0x838:0xFFF

Reserved

N/A

Overview of Configuration Space Register Fields

0x000

Device ID, Vendor ID

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x004

Status, Command

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x008

Class Code, Revision ID

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x00C

BIST, Header Type, Primary Latency Timer, Cache Line Size

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x010

Base Address 0

Base Address Registers

0x014

Base Address 1

Base Address Registers

0x018

Base Address 2

Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, Primary Bus Number

Base Address Registers

Secondary Latency Timer, Type 1 Configuration Space Header, Primary Bus Number

0x01C

Base Address 3

Secondary Status, I/O Limit, I/O Base

Base Address Registers

Secondary Status Register ,Type 1 Configuration Space Header

0x020

Base Address 4

Memory Limit, Memory Base

Base Address Registers

Type 1 Configuration Space Header

0x024

Base Address 5

Prefetchable Memory Limit, Prefetchable Memory Base

Base Address Registers

Prefetchable Memory Limit, Prefetchable Memory Base

0x028

Reserved

Prefetchable Base Upper 32 Bits

N/A

Type 1 Configuration Space Header

0x02C

Subsystem ID, Subsystem Vendor ID

Prefetchable Limit Upper 32 Bits

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x030

Expansion ROM base address

I/O Limit Upper 16 Bits, I/O Base Upper 16 Bits

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x034

Reserved, Capabilities PTR

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x038

Reserved

Expansion ROM Base Address

N/A

Type 1 Configuration Space Header

0x03C

Interrupt Pin, Interrupt Line

Bridge Control, Interrupt Pin, Interrupt Line

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x050

MSI-Message Control Next Cap Ptr Capability ID

MSI and MSI-X Capability Structures

0x054

Message Address

MSI and MSI-X Capability Structures

0x058

Message Upper Address

MSI and MSI-X Capability Structures

0x05C

Reserved Message Data

MSI and MSI-X Capability Structures

0x068

MSI-X Message Control Next Cap Ptr Capability ID

MSI and MSI-X Capability Structures

0x06C

MSI-X Table Offset BIR

MSI and MSI-X Capability Structures

0x070

Pending Bit Array (PBA) Offset BIR

MSI and MSI-X Capability Structures

0x078

Capabilities Register Next Cap PTR Cap ID

PCI Power Management Capability Structure

0x07C

Data PM Control/Status Bridge Extensions Power Management Status & Control

PCI Power Management Capability Structure

0x080

PCI Express Capabilities Register Next Cap Ptr PCI Express Cap ID

PCI Express Capability Structure

0x084

Device Capabilities Register

PCI Express Capability Structure

0x088

Device Status Register Device Control Register

PCI Express Capability Structure

0x08C

Link Capabilities Register

PCI Express Capability Structure

0x090

Link Status Register Link Control Register

PCI Express Capability Structure

0x094

Slot Capabilities Register

PCI Express Capability Structure

0x098

Slot Status Register Slot Control Register

PCI Express Capability Structure

0x09C

Root Capabilities Register Root Control Register

PCI Express Capability Structure

0x0A0

Root Status Register

PCI Express Capability Structure

0x0A4

Device Capabilities 2 Register

PCI Express Capability Structure

0x0A8

Device Status 2 Register Device Control 2 Register

PCI Express Capability Structure

0x0AC

Link Capabilities 2 Register

PCI Express Capability Structure

0x0B0

Link Status 2 Register Link Control 2 Register

PCI Express Capability Structure

0x0B4:0x0BC

Reserved

PCI Express Capability Structure

0x800

Advanced Error Reporting Enhanced Capability Header

Advanced Error Reporting Enhanced Capability Header

0x804

Uncorrectable Error Status Register

Uncorrectable Error Status Register

0x808

Uncorrectable Error Mask Register

Uncorrectable Error Mask Register

0x80C

Uncorrectable Error Severity Register

Uncorrectable Error Severity Register

0x810

Correctable Error Status Register

Correctable Error Status Register

0x814

Correctable Error Mask Register

Correctable Error Mask Register

0x818

Advanced Error Capabilities and Control Register

Advanced Error Capabilities and Control Register

0x81C

Header Log Register

Header Log Register

0x82C

Root Error Command

Root Error Command Register

0x830

Root Error Status

Root Error Status Register

0x834

Error Source Identification Register Correctable Error Source ID Register

Error Source Identification Register

Related Information
Level Two Title