Arria V Avalon-ST Interface for PCIe Solutions: User Guide

ID 683660
Date 5/12/2017
Document Table of Contents

15.2. Root Port Testbench

This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces of the Root Port and Endpoints or the serial PCI Express interface. The testbench design does not allow more than one PCI Express link to be simulated at a time. The top-level of the testbench instantiates four main modules:

  • <qsys_systemname>— Name of Root Port This is the example Root Port design. For more information about this module, refer to Root Port Design Example.
  • altpcietb_bfm_ep_example_chaining_pipen1b—This is the Endpoint PCI Express mode described in the section Chaining DMA Design Examples.
  • altpcietb_pipe_phy—There are eight instances of this module, one per lane. These modules connect the PIPE MAC layer interfaces of the Root Port and the Endpoint. The module mimics the behavior of the PIPE PHY layer to both MAC interfaces.
  • altpcietb_bfm_driver_rp—This module drives transactions to the Root Port BFM. This is the module that you modify to vary the transactions sent to the example Endpoint design or your own design. For more information about this module, see Test Driver Module.

The testbench has routines that perform the following tasks:

  • Generates the reference clock for the Endpoint at the required frequency.
  • Provides a reset at start up.
Note: Before running the testbench, you should set the following parameters:
  • serial_sim_hwtcl: Set this parameter in <instantiation name>_tb.v . This parameter controls whether the testbench simulates in PIPE mode or serial mode. When is set to 0, the simulation runs in PIPE mode; when set to 1, it runs in serial mode. Although the serial_sim_hwtcl parameter is available in other files, if you set this parameter at the lower level, it is overwritten by the tb.v level.
  • serial_sim_hwtcl: Set to 1 for serial simulation and 0 for PIPE simulation.
  • enable_pipe32_sim_hwtcl: Set to 0 for serial simulation and 1 for PIPE simulation.