Nios® V Processor Reference Manual

ID 683632
Date 8/01/2022

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Document Table of Contents

2.2. Processor Pipeline

The Nios V/m processor employs a five-stage pipeline.

Table 3.  Processor Pipeline Stages
Stage Denotation Function
F Instruction fetch
  • PC+4 calculation
  • Next instruction fetch
  • Pre-decode for register file read
D Instruction decode
  • Decode the instruction
  • Register file read data available
  • Hazard resolution and data forwarding
E Instruction execute
  • ALU operations
  • Memory address calculation
  • Branch resolution
  • CSR read/write
M emory
  • Memory and multicycle operations
  • Register file write
  • Branch redirection
W Write back
  • Facilitates data dependency resolution by providing general-purpose register value.

The Nios® V/m processor implements the general-purpose register file using the M20K memory blocks. The processor takes one processing cycle to read from an M20K location. Therefore, the F-stage initiates register file reads so general-purpose register values are available in D-stage.

Writing to the M20K location takes two processing cycles. Therefore, the M-stage initiates writes to a general-purpose register. If there is a dependency to resolve, the M-stage carries forward the value to the W-stage.

The core resolves data dependencies in the D-stage. Operands can move from register file read or E-stage, M-stage, or W-stage.

Reasons for the pipeline stalling:
  • Data dependency—if the source operand is not available in D-stage, instruction in D-stage and F-stage stalls until the operand becomes available. The scenario can happen if destination general-purpose register of load or multicycle instruction in E-stage or M-stage is the source for instruction in D-stage.
  • Resource stall—if a memory operation or multicycle is pending in M-stage, the instructions in preceding stages stalls until M-stage completes the instruction.