Nios® V Processor Reference Manual

ID 683632
Date 8/01/2022

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Document Table of Contents Debug Mode

You can enter the Debug Mode, as specified in the RISC-V architecture specification, in the following ways:

  1. Halt from Debug Module
  2. Software breakpoints
  3. Trigger
Upon entering Debug Mode, Nios® V processor completes the instruction in W-stage. By the order of priority, instruction in M-stage, E-stage, D-stage or F-stage takes the interrupt.
  • When there is a valid instruction, Program Counter writes to the Debug Program Counter, .dpc.

  • If the instruction in M-stage is not valid, then instruction in E-stage takes the interrupt and so on and so forth.

  • If there is no valid instruction in the pipeline, the Program Counter for the next instruction writes to the Debug Program Counter, .dpc.

Note: For branches, the next Program Counter depends on whether a branch was taken or not taken, and whether the branch prediction (if any) was correct.
Debug Module selects Hardware Thread (Hart); which can be in one of the following states:
  1. Non-existent: Debug Module probes a hart which does not exist.
  2. Unavailable: Reset or temporary shutdown.
  3. Running: Normal operation outside of debug.
  4. Halted: Hart is said to be halted when it is in debug mode.
Figure 3. Debug Module Block Diagram