Nios® V Processor Reference Manual

ID 683632
Date 8/01/2022

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Document Table of Contents

2.3.3. Reset and Debug Signals

Signal Name Type Description
reset Input This is a global hardware reset signal that forces the Nios® V processor core to reset immediately.
dbg_reset Output
The following are the characteristics of the reset output signal:
  • Visible when you enable the option Enable Debug.
  • Triggered by the GNU debugger (GDB) or niosv-download -r command
  • Internally routed to the Nios® V processor core and timer module. This allows the JTAG debugger to reset the processor and the timer module.
  • Can be connected to the reset input signal of other components as needed.
reset_req Input
  • You can request a reset to the Nios® V processor core by asserting the reset_req signal.
  • The reset_req signal must remain asserted until the processor asserts reset_req_ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
  • Assertion of the reset_req signal in debug mode has no effect on the processor's state.
reset_req_ack Output
  • The Nios® V processor responds that the reset is successful by asserting the reset_req_ack signal.
  • After the processor is successfully reset, the assertion of the reset_req_ack signal can happen multiple times periodically until the de-assertion of the reset_req signal.