Nios® V Processor Reference Manual

ID 683632
Date 8/01/2022

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Document Table of Contents

2.1. Processor Performance Benchmarks

Table 1.   Nios® V/m Processor Performance Benchmarks in Intel FPGA Devices
FPGA Used fMAX (MHz) Logic Size (ALM) Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® 10 270.27 1375 0.463 0.31365
Intel® Arria® 10 305.62 1375
Intel® Stratix® 10 361.93 1580
Intel® Agilex™ 566.25 1509
Table 2.  Benchmark Parameters
Parameter Settings/Description
Intel® Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Pro Edition software version 21.3.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/m processor core
  • 4 KB on-chip memory for the instruction bus
  • 4 KB on-chip memory for data bus
  • Avalon® Memory-Mapped Pipeline Bridge
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 11.2.0
  • CMake Version: 3.23.1
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32ia -mabi=ilp32
Intel uses the same Intel® Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. However, the compiler settings are different for each benchmarks:
  • fMAX benchmark: superior_performance_optimized_placement_effort
  • Logic size benchmark: area_aggressive
Note: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.