Nios® V Processor Reference Manual

ID 683632
Date 8/01/2022

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2.3.5. Exception Controller

The Nios® V/m processor architecture provides a simple exception controller to handle all exception types. Each exception, including internal hardware interrupts, causes the processor to transfer execution to an exception address. An exception handler at this address determines the cause of the exception and executes an appropriate exception routine. You can set the exception address in the Nios® V/m Processor IP Parameter Editor. Nios® V/m processor stores the address, which is writable, in machine trap handler base address (mtvec) CSR register.

All exceptions are precise. The processor completes all instructions that precede the faulting instruction and does not start the execution of instructions that follow after the faulting instruction.

Table 5.  Exceptions
Exception Description
Instruction Address Misaligned The core pipeline logic in F-stage detects the exception. This exception is flagged if the core fetched a program counter that is not aligned to a 32-bit word boundary.
Instruction Access Fault The instruction read response signal detects this exception.
Illegal Instruction The instruction decoder in the D-stage flags this exception if an instruction word contains encoding for an unimplemented or undefined instruction.

The control logic for the CSR read and write flags this exception in the E-stage if a CSR instruction accesses a CSR that is not implemented or undefined.

Breakpoint The instruction decoder flags the software breakpoint exception EBREAK in the D-stage.
Load Address Misaligned The core for the load/store unit in the M-stage detects the misalignment. This exception is flagged if the data address is not aligned to the size of the data access.
Store Address Misaligned
Load Access Fault The core for the data read and write response signal detects the exception.
Store Access Fault
Env call from M-mode The instruction decoder in the D-stage detects the instruction.