AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

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ID 683624
Date 1/29/2020
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Document Table of Contents
Document Table of Contents x
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission x
1.1. PCB Material Selection 1.2. Stackup Design 1.3. Channel Design 1.4. Summary 1.5. Document Revision History for the AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1.1. PCB Material Selection x
1.1.1. Loss Tangent and Dissipation Factor 1.1.2. Dielectric Constant 1.1.3. Fiberglass Weave 1.1.4. Copper Surface Roughness
1.3. Channel Design x
1.3.1. BGA Channel Breakout 1.3.2. Channel Routing Design 1.3.3. Edge Coupling 1.3.4. Broadside Coupling 1.3.5. Transparent Via Design 1.3.6. Blocking Cap Optimization 1.3.7. Connectors Optimization
1.3.2. Channel Routing Design x
1.3.2.1. Trace Width Selection 1.3.2.2. Loose vs. Tight Coupled Traces 1.3.2.3. Crosstalk Control
1.4. Summary x
1.4.1. PCB Material Selection 1.4.2. Stackup Design 1.4.3. Channel Design 1.4.4. References
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

1.1.2. Dielectric Constant

The dielectric Constant (Ɛr or Dk in many material data sheets) is a measure of the insulating properties of the material and affects the capacitance of the conductor embedded within it as well as the speed of signal propagation on the transmission line. Lower dielectric constant provides better insulation, faster signal propagation, higher trace impedance for a given trace geometry and smaller stray capacitance.

Figure 3.  Stripline Differential Trace

Stripline Differential Trace

Table 1.   100-Ω Stripline FR4 vs. Megtron-6 Construction
Material Er W (mils) S (mils) T (mils) H1 (mils) H2 (mils) Zo (Ω) Zdiff (Ω) Tpd (ps/in) C (pF/in)
FR4 4.6 6 15 0.7 7 11 52 100 182 3.5
Meg-6 3.4 6 15 0.7 5 8 100 156 3.1

Consider a 100-Ω differential stripline pair constructed with an optimal trace width (W) of 6 mils and pair separation (S) of 15 mils. For FR4, the total dielectric thickness is 18.7 mils (T+H1+H2). For the same trace construction dimensions using Megtron-6 the total thickness is 13.7 mils. This reduction of total thickness by 5 mils is significant because it quickly adds up for high density boards that require many signal layers. For instance, a typical FPGA board with 6 stripline routing layers can result in 30 mils of PCB thickness savings using the Megtron 6 vs. FR4. This can be the difference between boards that are easily manufactured using standard via drilling processes vs. ones that require more expensive laser drilling techniques because of the smaller board thickness to via aspect ratio. Furthermore, lower Ɛr results in faster signal propagation (Tpd) and lower trace capacitance (C), which improves signal performance.

An additional consideration for Ɛr is that it usually decreases as frequency increases. Decreasing Ɛr affects the transmission line in two ways:

  • The trace impedance increases with decreasing Ɛr causing reflections that further degrade signal quality
  • The signal velocity increases with decreasing Ɛr causing dispersion of the different harmonics that comprise the digital signal. This results in increased phase jitter at the receiver
Note: Always choose lower Ɛr with a flat frequency response for best signal performance and to reduce signal dispersion that adds phase jitter.
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