AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

ID 683624
Date 1/29/2020

1.3.5. Transparent Via Design

Unless you are routing all transceiver channels with only microstrip traces on the top layer, you must use vias in the design to transition layers. Unfortunately, the characteristic impedance of differential vias are lower than 100 Ω. Generally it is in the range of 80 to 85 Ω. This impedance mismatch causes reflections that degrade the channel performance. To better match the impedance of the via with the 100 Ω differential traces requires optimization techniques that minimize the parasitic capacitance (Cvia) and inductance (Lvia) of the via.

Tip: You can minimize Cvia using the following optimization techniques:
  • Reduce the via capture pad size
  • Eliminate all non-functional pads (NFP)
  • Increase the via anti-pad size to 40 or 50 mils
Tip: You can minimize Lvia using the following optimization techniques:
  • Eliminate and / or reduce via stubs
  • Minimize via barrel length by routing the stripline traces near the top surface layer and applying backdrilling

For example, consider an 8-layer PCB board that uses standard via with 10-mil drill diameter, 20-mil capture pad diameter, and 30-mil anti-pad diameter. Optimizing this via by successively applying the techniques above to minimize Cvia and Lvia improves the impedance of the via, and its insertion and return loss.

Figure 21.  TDR of Standard vs. Optimized Via

TDR of Standard vs. Optimized Via

Figure 22.  Insertion and Return Loss of Standard vs. Optimized Via

Insertion and Return Loss of Standard vs. Optimized Via

Additional improvements besides minimizing Cvia and Lvia involves providing a better AC return path by adding a ground via next to each signal via as well as applying backdrilling to remove any left over via stub.

Note: Add ground return vias within 35 mils of each signal via to further improve the insertion and return losses of the via.