AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

Download PDF
ID 683624
Date 1/29/2020
Public
Document Table of Contents
Document Table of Contents x
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission x
1.1. PCB Material Selection 1.2. Stackup Design 1.3. Channel Design 1.4. Summary 1.5. Document Revision History for the AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission
1.1. PCB Material Selection x
1.1.1. Loss Tangent and Dissipation Factor 1.1.2. Dielectric Constant 1.1.3. Fiberglass Weave 1.1.4. Copper Surface Roughness
1.3. Channel Design x
1.3.1. BGA Channel Breakout 1.3.2. Channel Routing Design 1.3.3. Edge Coupling 1.3.4. Broadside Coupling 1.3.5. Transparent Via Design 1.3.6. Blocking Cap Optimization 1.3.7. Connectors Optimization
1.3.2. Channel Routing Design x
1.3.2.1. Trace Width Selection 1.3.2.2. Loose vs. Tight Coupled Traces 1.3.2.3. Crosstalk Control
1.4. Summary x
1.4.1. PCB Material Selection 1.4.2. Stackup Design 1.4.3. Channel Design 1.4.4. References
1. AN 672: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission

1.4.3. Channel Design

  • For high-speed transceiver signals, use trace widths of 6mils or more to minimize conductor loss.
  • Limit use of 4-mil trace widths to the BGA breakout area and keep their trace length as short as possible.
  • Loosely coupled traces are easier to route and maintain impedance control but take up more routing area.
  • Tightly coupled traces saves routing space but can be difficult to control impedance.
  • Use stripline routing to avoid FEXT concerns.
  • Use stripline traces with 5H differential pair-to-pair separation to minimize NEXT to 1%.
  • If microstrip routing is required, used 6H-7H differential pair-to-pair separation to avoid NEXT and FEXT issues.
  • Cvia optimization techniques
    • Reduce the via capture pad size
    • Eliminate all non-functional pads (NFP)
    • Increase the via anti-pad size to 40 or 50 mils
  • Lvia optimization techniques:
    • Eliminate and / or reduce via stubs
    • Minimize via barrel length by routing near the stripline traces near the top surface layer and applying backdrilling
  • Add ground return vias within 35 mils of each signal via to further improve the insertion and return losses of the via.
  • Use manufacturer layout recommendations for connectors if available. In absence of any specific manufacturer recommendations, designers can apply the transparent via optimization and DC blocking capacitor compensation.
Level Two Title