Intel® Quartus® Prime Pro Edition User Guide: Platform Designer
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7.1.2. Avalon® Memory Mapped Clock Crossing Bridge Intel® FPGA IP
The Avalon® Memory Mapped Clock Crossing Bridge uses asynchronous FIFOs to implement clock crossing logic. The bridge parameters control the depth of the command and response FIFOs in both the host and agent clock domains. If the number of active reads exceeds the depth of the response FIFO, the Clock Crossing Bridge stops sending reads.
To maintain throughput for high-performance applications, increase the response FIFO depth from the default minimum depth, which is twice the maximum burst size.