Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/03/2023
Public

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Document Table of Contents

2.1. What's New In This Version

  • Intel Agilex® 7 M-Series FPGAs support an integrated Network-on-Chip (NoC) to facilitate high-bandwidth data movement between the FPGA core logic and memory resources, such as HBM2e and DDR5 memories. You can make connections between NoC IP elements and generate NoC simulation files in Platform Designer, as Connecting NoC IP in Platform Designer and Generating Simulation Files for NoC Designs describe.
  • There is a new get_quartus_instance_path_for_entity Tcl API, as Board-Aware Flow Scripting Support describes.
  • There is no support for fixed-latency pipelined read transfers to the Avalon Memory Mapped Pipeline Bridge, as Avalon® Memory Mapped Pipeline Bridge Intel® FPGA IP describes.
  • The Name HDL Signals for Automatic Interface and Type Recognition function is currently unsupported and references are removed from this document.
  • The product family name is updated to Intel Agilex® 7 FPGAs to reflect the different family members.
  • For change details, refer to the chapter revision histories in this document.