Intel® Quartus® Prime Pro Edition User Guide: Platform Designer
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Ixiasoft
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Ixiasoft
6.10.9.1. Transaction Cannot Cross 4KB Boundaries
When connecting an Avalon® memory-mapped interface FPGA host to an AXI subordinate in Platform Designer, you must ensure that the bursts do not exceed the AXI3 or AXI4 4KB boundary restriction for burst transactions.