Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/03/2023
Public

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2.18.3. Generating Simulation Files NoC Designs

Intel Agilex® 7 M-Series FPGAs support an integrated Network-on-Chip (NoC) to facilitate high-bandwidth data movement between the FPGA core logic and memory resources, such as HBM2e and DDR5 memories.

In addition, behavioral, non-cycle accurate simulation of the NoC is available, in combination with your logic as either RTL or as a functional (non-timing) gate-level netlist. You can use these simulation methods to verify correct specification of the connectivity and addressing. However, you cannot model the traffic congestion on the hard memory NoC.

To describe connectivity and address mapping for simulation, each NoC initiator-to-target connection requires a registration statement. The registration statement specifies the start address and the size of the connection address range.

You can generate a simulation include file that includes these registration statements. As part of the regular compilation flow, this include file generates after running Analysis & Elaboration and specifying NoC connectivity and addressing in the NoC Assignment Editor. An optional early RTL simulation flow is available that does not require running Analysis & Elaboration. In this flow, you can use Platform Designer to generate a registration include file for simulation after specifying the NoC connectivity and addressing in Platform Designer. As with any other Intel FPGA IP, you can use Platform Designer to generate simulation models for NoC-related IP during IP HDL generation, along with the registration include file.

For detailed information on NoC simulation, refer to Intel Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide.