Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/03/2023
Public

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2. Creating a System with Platform Designer

The Intel® Quartus® Prime software includes the Platform Designer system integration tool. Platform Designer simplifies the task of defining and integrating custom IP components (IP cores) into your FPGA design.

Platform Designer automatically creates interconnect logic from high-level connectivity that you specify. The interconnect automation eliminates the time-consuming task of specifying system-level HDL connections.

Figure 1.  Platform Designer GUI

Platform Designer allows you to specify interface requirements and integrate IP components within a graphical representation of the system. The Intel® Quartus® Prime software installation includes the Intel FPGA IP library available from the IP Catalog in Platform Designer.

You can integrate optimized and verified Intel FPGA IP cores into a design to shorten design cycles and maximize performance. Platform Designer also supports integration of IP cores from third-parties, or custom components that you define.

Platform Designer supports a hierarchical framework that offers fast response times for interconnecting large systems and blackbox entities. Platform Designer supports a variety of design entry methods, such as register transfer level (RTL) and schematic entry. Platform Designer supports the creation of your own custom components, as well as generic components that define only the interface and signal connections to the rest of the system.

Platform Designer provides support for the following:

  • Create and reuse components—define and reuse custom parameterizable components in a Hardware Component Definition File (_hw.tcl) that describes and packages IP components.
  • Define generic IP components—instantiate generic IP components without an HDL implementation.
  • Incremental generation—optimize and generate IP components incrementally.
  • Avalon® to AXI interconnect—Platform Designer generates appropriate types of interconnect logic to handle protocol differences.
  • Hierarchical system support—generates a separate .ip file that isolates the system from the IP component parameterization. Change parameters of a single IP component without regeneration of other IP components.
  • Command-line support—optionally use command-line utilities and scripts to perform functions available in the Platform Designer GUI.
  • Up to 64-bit addressing.
  • Optimization of interconnect and pipelining within the system and auto-adaptation of data widths and burst characteristics.
  • Inter-operation between standard protocols.