E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 3/06/2022
Public

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2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide

The E-tile Hard IP for Ethernet Intel® FPGA IP core for Intel® Stratix® 10 devices provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

In addition, you can download the compiled hardware design to the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit. Intel® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

Table 1.  List of Supported Design Example Variants
Data Rate Variant Simulation Compilation-Only Project Hardware Design Example
10GE Single or multi channels Media Access Controller (MAC) + Physical Coding Sublayer (PCS) with optional 1588 Precision Time Protocol (PTP)
Single channel PCS
Single channel Optical Transport Network (OTN) X
Single channel Flexible Ethernet (FlexE) X
Single or multi channels custom PCS
25GE
Single or multi channels MAC + PCS with optional RS-FEC and optional PTP
  • Asynchronous Adapter clock
Single channel PCS with optional RS-FEC
Single channel OTN with optional RS-FEC X
Single channel FlexE with optional RS-FEC X
Single or multi channels custom PCS with optional RS-FEC
100GE MAC+ PCS with optional:
  • (528,514) RS-FEC
  • PTP
MAC+PCS with (544, 514) RS-FEC
PCS with optional (528,514) or (544, 514) RS-FEC
OTN with optional (528,514) or (544, 514) RS-FEC X
FlexE with optional (528,514) or (544, 514) RS-FEC X
Figure 1. Development Steps for the Design ExampleThe compilation-only example project cannot be configured in hardware.

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