E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 3/06/2022

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Document Table of Contents

3.1.6. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Intel® Stratix® 10 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project <design_example_dir>/hardware_test_design/alt_cpriphy_c3_hw.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in <design_example_dir>/hardware_test_design/output_files directory. Follow these steps to program the hardware design example on the Intel® Stratix® 10 device:
    1. Connect Intel® Stratix® 10 Transceiver Signal Integrity Development Kit to the host computer.
    2. Launch the Clock Control application, which is part of the development kit, and set new frequencies for the design example. Below is the frequency setting in the Clock Control application:
      • Y1—156.25 MHz
      • U3, OUT3—100 MHz
      • U3, OUT5— Set this value to 184.32 MHz for the CPRI designs that target 10.1, 12.1 and 24.3 Gbps (with and without RS-FEC) line rates and 153.6 MHz for the CPRI designs that target 2.4/3/4.9/6.1/9.8 Gbps CPRI line rates.
    3. On the Tools menu, click Programmer.
    4. In the Programmer, click Hardware Setup.
    5. Select a programming device.
    6. Select and add the Stratix 10 TX Transceiver Signal Integrity Development kit to which your Intel® Quartus® Prime Pro Edition session can connect.
    7. Ensure that Mode is set to JTAG.
    8. Select the Intel® Stratix® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    9. In the row with your .sof, check the box for the .sof.
    10. Check the box in the Program/Configure column.
    11. Click Start.