E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 3/06/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.5.4. 100GE DR Hardware Design Examples

This section describes high-level flow guidelines for the E-tile reconfigurable Ethernet core.

You can follow these steps to configure the E-tile reconfigurable Ethernet IP core:
  1. Create a hardware project.
    • Instantiate the E-Tile Dynamic Reconfiguration Design Example for 100G Ethernet protocol.
    • Configure the IP parameters and generate design in the Intel® Quartus® Prime.
  2. Reconfigure the hardware project as needed during the run time.
    • Define next configuration by programing CSR registers.
    • Trigger the reconfiguration. Both variants, four 25G and one 100G Ethernet, are supported.
    • Repeat step 2.