E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 3/06/2022
Public

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Document Table of Contents

2.5. Document Revision History for the E-Tile Hard IP for Ethernet Intel FPGA IP Design Example

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.11.22 21.3 20.2.1
  • Added support for Questa* simulator.
  • Removed support for NCSim simulator.
2021.04.28 20.4 20.2.0 Added a new section:Ethernet Toolkit Overview.
2020.12.14 20.2 20.2.0
  • Added a command to select the JTAG master in the following sections::
    • 100GE MAC+PCS with Optional (528,514) RS-FEC or (544,514) RS-FEC and Adaptation Flow Hardware Design Example
    • 100GE PCS Only with Optional (528,514) RS-FEC or (544,514) RS-FEC, and Optional PTP Hardware Design Example
  • Added EnhancedPTPAccuracy command setting and its description in 10GE/25GE Design Example section.
2020.06.29 20.2 20.2.0
  • Revised Y1 description in the Compiling and Configuring the Design Example in Hardware section.
2019.12.23 19.4 19.4.0
  • Updated description of PMA adaptation setting in the Generating the Design section.
  • Added Asynchronous clock support for the 100GE MAC+PCS with (528,514) RS-FEC and PTP variant.
  • Restructured topics to improve the content flow.
2019.09.30 19.3 19.3.0
  • Updated the List of Supported Design Example Variants table in E-tile Hard IP for Ethernet Intel FPGA IP Quick Start Guide:
    • Added support for Single or multi channels custom PCS with optional RS-FEC for 10GE variant.
    • Removed Asynchronous clock support from the 100GE MAC+PCS with (528,514) RS-FEC and PTP variant
    • Added support for 100GE MAC+PCS with (544,514) RS-REC variant
  • Updated Generated the Design section:
    • Replaced external loopback with external link partner connection.
    • Added Stratix 10 TX Transceiver Signal Integrity Development Kit-1ST280EY2F55E2VGSI and Stratix 10 TX Transceiver Signal Integrity Development Kit-1ST280EY2F55E2VG under the Target Development Kit board selection.
  • Added a note to clarify run_vcs.sh and run_vcsmx.sh usage in the Steps to Simulate the Testbench table.
  • Updated the List of Supported Design Example Variants for 10G/25GE table in 10GE/25GE with Optional RS-FEC Design Examples.
  • Updated register name Source address upper, 16 bits in the Packet Client Register table for all variants.
2019.05.17 19.1 19.1
  • Renamed the document as E-tile Hard IP Intel® Stratix® 10 Design Examples User Guide.
  • Added 10GE/25GE custom PCS with optional RS-FEC simulation, compilation-only project, and hardware design examples.
  • Added E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with optional RS-FEC and PTP simulation, compilation-only project, and hardware design examples.
  • Updated the Testing the E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Example topic:
    • Added a new subtopic: 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example.
    • Updated the 10GE/25GE MAC+PCS with Optional RS-FEC and Optional PTP Hardware Design Example and 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example subtopics.
    • Updated the following commands in the 100GE MAC+PCS with Optional (528,514) RS-FEC and PMA Calibration Hardware Design Example and 100GE MAC+PCS with Optional (544,514) RS-FEC and PMA Calibration Hardware Design Example topics:
      • start_pma_init_adaptation
      • start_pma_anlg_rst03
      • init_adaptation_16_NoPrbsNoLdEL03
      • chk_init_adaptation_status
      • chk_init_adaptation_status_02
    • Updated Figure: In-System Sources and Probes Editor in the following topics:
      • 10GE/25GE MAC+PCS with Optional RS-FEC and Optional PTP Hardware Design Example
      • 10GE/25GE PCS Only with Optional RS-FEC Hardware Design Example
      • 10GE/25GE Custom PCS with Optional RS-FEC Hardware Design Example
  • Updated Table: List of Supported Design Example Variants.
  • Updated Table: Packet Generator and Checker Registers of the 100GE PCS with Optional RS-FEC Design Example Registers topic to update the register names for address 0xF000 and 0xF001.
  • Updated the following Figures:
    • Simulation Block Diagram for Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 10GE/25GE MAC+PCS with Optional RS-FEC Design Example.
    • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 10GE/25GE with Optional RS-FEC and PTP Design Example.
    • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 10GE/25GE with Optional RS-FEC and PTP Design Example.
  • Updated the 10GE/25GE with Optional RS-FEC Design Example chapter:
    • Updated Table: Supported Design Example Variants for 10GE/25GE.
    • Updated the following simulation design example topics:
      • Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
      • 10GE/25GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
      • 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
      • 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
    • Added new Table: Packet Generator Registers.
  • Updated the 100GE with Optional RS-FEC Design Example chapter:
    • Updated the following simulation design example topics:
      • Non-PTP E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Simulation Design Example.
      • E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
      • E-Tile Hard IP for Ethernet Intel FPGA IP 100GE PCS Only with Optional RS-FEC Simulation Design Example
      • E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN with Optional RS-FEC Simulation Design Example
      • E-Tile Hard IP for Ethernet Intel FPGA IP 100GE FlexE with Optional RS-FEC Simulation Design Example
    • Updated the following Figures:
      • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 100GE MAC+PCS with Optional RS-FEC Design Example.
      • Simulation Block Diagram for E-Tile Hard IP for Ethernet Intel FPGA IP 100GE OTN Design Example.
  • Made editorial updates throughout the document.
2019.02.14 18.1.1 18.1.1 Updated Table: Steps to Simulate the Testbench to include instruction for Xcelium simulator.
2019.01.04 18.1.1 18.1.1
  • Added information for the following design examples:
    • 10GE/25GE PCS Only, OTN, and FlexE RSFEC simulation and compilation-only project design examples.
    • 10GE/25GE PCS Only hardware design example.
    • Multi channel 10GE/25GE MAC + PCS with optional RSFEC and PTP simulation, compilation-only project, and hardware design examples.
    • 100GE MAC + PCS with optional RSFEC(544,514) simulation, compilation-only project, and hardware design examples.
    • 100GE PCS Only with optional RSFEC(528,514) and RSFEC(544,514) simulation, compilation-only, and hardware design examples.
  • Updated steps to test 10GE/25GE MAC + PCS with optional RSFEC and optional PTP and 100GE MAC+PCS with optional RSFEC and PMA calibration hardware design examples.
  • Updated result log for 10GE/25GE MAC + PCS with optional RSFEC and optional PTP and 100GE MAC+PCS with optional RSFEC and PMA calibration hardware design examples.
  • Updated simulation and hardware design example block diagram for 10GE/25GE MAC + PCS with optional RSFEC and non-PTP 10GE/25GE MAC + PCS with optional RSFEC variants.
  • Updated register map for 10GE/25GE and 100GE design examples.
2018.08.10 18.0 18.0
Added a note to clarify that the E-Tile Hard IP for Ethernet Intel FPGA IP provides preliminary support for the OTN feature in the following sections:
  • Quick Start Guide
  • 100GE with Optional RSFEC Design Example
  • 100GE OTN Simulation Design Example
2018.07.19 18.0 18.0 Initial release.