AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683560
Date 9/24/2018
Public
Document Table of Contents

1.3.1.3.5. Partial Reconfiguration Logic

The reference design provides the following personas:

Table 6.  Reference Design Personas
Persona Description
DDR4 access

Performs a sweep across a memory span, first writing, and then reading each address.

Basic DSP

Provides access to a 27x27 DSP multiplier, and demonstrates hardware acceleration.

Basic arithmetic

Includes a basic 32-bit unsigned adder, and demonstrates hardware acceleration.

Game of Life

Includes an 8x8 Conway's Game of Life, and demonstrates hardware acceleration.

Each persona has an 8-bit persona_id field in the pr_data register to indicate a unique identification number. A 32-bit control register and 16 I/O registers follow the 8-bit persona_id. The 16 I/O registers are 32-bit each, with 8 bits for device inputs, and 8 bits for device outputs. Each persona uses these registers in different ways. For more information, refer to the source code for each of the personas.

Additionally, the reference design provides a template to implement your custom persona. This template persona allows you modify the RTL, create a wrapper to interface with the register file, compile, and run your design.

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