Visible to Intel only — GUID: frd1512684701052
Ixiasoft
Visible to Intel only — GUID: frd1512684701052
Ixiasoft
1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
Updated for: |
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Intel® Quartus® Prime Design Suite 18.1 |
Partial reconfiguration allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design, without impacting operation in areas outside this region. Partial reconfiguration enables the implementation of more complex FPGA systems.
- Allows run-time design reconfiguration
- Increases scalability of the design through time-multiplexing
- Lowers cost and power consumption through efficient use of board space
- Supports dynamic time-multiplexing functions in the design
- Improves initial programming time through smaller bitstreams
- Reduces system down-time through line upgrades
- Enables easy system update by allowing remote hardware change
Intel® Quartus® Prime Pro Edition software v.18.1 introduces a new and simplified compilation flow for partial reconfiguration.
Section Content
Reference Design Overview
Getting Started
Reference Design Components
Compiling the Reference Design
Testing the Reference Design
Extending the Reference Design with Custom Persona
Document Revision History for AN 819: Partial Reconfiguration over PCI Express Reference Design for Intel Stratix 10 Devices
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