AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683560
Date 9/24/2018
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Document Table of Contents

1. Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

Updated for:
Intel® Quartus® Prime Design Suite 18.1
The Partial Reconfiguration (PR) over PCI Express* ( PCIe* ) reference design demonstrates reconfiguring the FPGA fabric through the PCIe* link in Intel® Stratix® 10 devices. This reference design runs on a Linux system with the Intel® Stratix® 10 GX FPGA development board. Adapt this reference design to your requirements by implementing the PR region logic using the given template. Run your custom design on this fully functional system that enables communication over PCIe* .

Partial reconfiguration allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design, without impacting operation in areas outside this region. Partial reconfiguration enables the implementation of more complex FPGA systems.

Partial reconfiguration provides the following advancements to a flat design:
  • Allows run-time design reconfiguration
  • Increases scalability of the design through time-multiplexing
  • Lowers cost and power consumption through efficient use of board space
  • Supports dynamic time-multiplexing functions in the design
  • Improves initial programming time through smaller bitstreams
  • Reduces system down-time through line upgrades
  • Enables easy system update by allowing remote hardware change

Intel® Quartus® Prime Pro Edition software v.18.1 introduces a new and simplified compilation flow for partial reconfiguration.

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