AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683560
Date 9/24/2018
Document Table of Contents Design Top

This component forms the core of the design, and includes the following:
  • Reset logic
  • PR region
  • Partial Reconfiguration IP core
  • Clock crossing and pipe-lining for Avalon MM Transactions
  • System description ROM
  • PLL