1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
1.1.1. Clocking Scheme
The reference design creates a separate Altera IOPLL IP core-generated clock. This clock creation decouples the PR logic clocking from both the PCIe* clocking domain that runs at 125 MHz, and the EMIF clocking domain that runs at 233 MHz. The clock for PR Logic is set at 125 MHz. To ensure timing closure, modify the parameterization of the IOPLL IP core to a lower clock frequency.
Figure 2. Timing Closure
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