AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683560
Date 9/24/2018
Document Table of Contents

1.2.4. Bringing Up the Reference Design

The reference design is available in the following location:

To access the reference design, navigate to the ref_designs sub-folder. Copy the s10_pcie_devkit_pr folder to the home directory in your Linux system.

Before you begin: You must at least compile the base revision of the design.

To bring up the reference design on the board:
  1. Plug-in the Intel® Stratix® 10 GX FPGA development board to an available PCIe* slot in your host machine.
  2. Connect the host machine's ATX auxiliary power connector to the 12 V ATX input J4 of the development board.
  3. Power-up the host machine.
  4. Verify the micro-USB cable connection to the FPGA development board. Ensure that no other applications that use the JTAG chain are running.
  5. Navigate to the s10_pcie_devkit_pr/software/installation folder in your system.
  6. This reference design uses a lower frequency memory reference clock than the default configuration on the device. To configure the memory reference clock to the correct frequency:
    1. Open the Intel® Quartus® Prime software and click Tools > Programmer.
    2. Use the max5_116.pof file in the s10_pcie_devkit_pr/software/installation directory to flash the MAX® V device on the Intel® Stratix® 10 GX FPGA Development Kit.
  7. Ensure that the DIP switch 1 is configured with both jumpers in the UP position.
    Important: Perform the above step only if you are bringing up the design for the first time. Otherwise, you can skip this step.
  8. To overwrite the existing factory image on the board with the reference design, execute the script.
  9. Pass the JTAG cable number of your connected device as an argument to the script. (for example, perl 1)
    Running this script configures the device with the contents of the flash.pof file. This parallel object file comes directly from the s10_pcie_devkit_pr.sof file present in the output_files directory. The flash.pof file acts as the base image for the reference design.
    Note: Ensure successful compilation of the design before running this script.
  10. Turn-off the machine, reset DIP switch 1 to move the jumpers to the default position (UP, DOWN), and then turn-on the machine.
    Important: Perform the above step only if you are bringing up the design for the first time. Otherwise, you can simply power-cycle the host machine.