1.1. Reference Design Overview 1.2. Getting Started 1.3. Reference Design Components 1.4. Compiling the Reference Design 1.5. Testing the Reference Design 1.6. Extending the Reference Design with Custom Persona 1.7. Document Revision History for AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices
1.2.1. Hardware and Software Requirements
The reference design requires and uses the following hardware and software tools:
- Intel® Stratix® 10 GX FPGA development board with the DDR4 module connected to Hi-Lo interface
- Linux Operating System - kernel version 3.10 or above
- Super user access on the host machine
- PCIe* slot to plug-in the Intel® Stratix® 10 GX FPGA development board
- Open source driver for this PR over PCIe* reference design
- Intel® Quartus® Prime Pro Edition software v.18.1
- Intel® FPGA Download Cable driver
- The Linux driver accompanying this reference design is not a production driver. You must adapt this driver to your design’s strategy to handle backpressure from the Intel® Stratix® 10 Partial Reconfiguration IP core.
- This reference design works under the assumption that the PCIe* link does not require a 100 ms initialization time.
Note: The open source driver developed for this PR over PCIe* reference design is tested using CentOS 7.
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