AN 819: Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683560
Date 9/24/2018
Public
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1.5.3.2. Programming the Design Using Example Applications

The following steps describe programming your design using the provided scripts:

  1. To program the DDR access persona’s .sof file after design compilation, type the following from the Linux shell:
    program-fpga-jtag -f=s10_pcie_devkit_cvp_ddr4_access.sof -c=1 -i=1
  2. To verify the functionality of the design, type the following from the Linux shell:
    ./example_host_uio
  3. To program the basic DSP persona’s .rbf file after design compilation, type the following from the Linux shell:
    fpga-configure -p s10_pcie_devkit_cvp_basic_dsp.pr_partition.rbf 10000
  4. To verify the functionality of the design, type the following from the Linux shell:
    ./example_host_uio
  5. To program the basic arithmetic persona’s .rbf file after design compilation, type the following from the Linux shell:
    fpga-configure -p s10_pcie_devkit_cvp_basic_arithmetic.pr_partition.rbf 10000
  6. To verify the functionality of the design, type the following from the Linux shell:
    ./example_host_uio
  7. To program the Game of Life persona's .rbf file after design compilation, type the following from the Linux shell:
    fpga-configure -p s10_pcie_devkit_cvp_gol.pr_partition.rbf 10000
  8. To verify the functionality of the design, type the following from the Linux shell:
    ./example_host_uio -v