Advanced SEU Detection Intel® FPGA IP User Guide

Download
ID 683542
Date 3/26/2019
Public
Document Table of Contents

1. Advanced SEU Detection Intel® FPGA IP Overview

Updated for:
Intel® Quartus® Prime Design Suite 18.1

The Advanced SEU Detection IP core enables you to perform:

  • Hierarchy tagging—Allows you to describe the criticality of each portion of your design's hierarchy relative to single event upset (SEU). You perform hierarchy tagging during the design phase.
  • Sensitivity processing—Determines the criticality of an SEU detected and located by error detection cyclical redundancy check (EDCRC) hard IP. This feature includes on- and off-chip sensitivity processing. The system performs sensitivity processing at runtime.
Table 1.  Features Device Family Support
Feature Supported Devices
Hierarchy Tagging and Sensitivity Processing Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, Arria® V, and Cyclone® V.
Sensitivity Processing Stratix® IV, Arria® II GX, and Arria® II GZ.

You can select and configure the Advanced SEU Detection IP core through the IP Catalog and parameter editor in the Intel® Quartus® Prime software.

The Advanced SEU Detection IP core must be used along with the EMR Unloader Intel® FPGA IP core. The EMR Unloader IP core provides Error Message Register (EMR) contents whenever it detects an EDCRC error. Connect the emr, emr_valid and emr_error signals from your EMR Unloader IP variation to the corresponding inputs of your Advanced SEU Detection variation.

Did you find the information on this page useful?

Characters remaining:

Feedback Message