Advanced SEU Detection Intel® FPGA IP User Guide

ID 683542
Date 3/26/2019
Public
Document Table of Contents

3.1.2. The Parameter Editor

The parameter editor helps you to configure IP core ports, parameters, and output file generation options. The basic parameter editor controls include the following:
  • Use the Presets window to apply preset parameter values for specific applications (for select cores).
  • Use the Details window to view port and parameter descriptions, and click links to documentation.
  • Click Generate > Generate Testbench System to generate a testbench system (for select cores).
  • Click Generate > Generate Example Design to generate an example design (for select cores).
  • Click Validate System Integrity to validate a system's generic components against companion files. (Platform Designer systems only)
  • Click Sync All System Info to validate a system's generic components against companion files. (Platform Designer systems only)

The IP Catalog is also available in Platform Designer (View > IP Catalog). The Platform Designer IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Intel® Quartus® Prime IP Catalog. Refer to Creating a System with Platform Designer or Creating a System with Platform Designer (Standard) for information on use of IP in Platform Designer (Standard) and Platform Designer, respectively.