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Ixiasoft
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Ixiasoft
4.2. Hierarchy Tagging
The Quartus® Prime hierarchy tagging feature enables customized soft error classification by indicating design logic susceptible to soft errors. Hierarchy tagging improves design-effective FIT rate by tagging only the critical logic for device operation. You also define the system recovery procedure based on knowledge of logic impaired by SEU. This technique reduces downtime for the FPGA and the system in which the FPGA resides. The Arria® 10, Cyclone® 10 GX, Stratix® V, Arria® V, and Cyclone® V devices support hierarchy tagging.
The .smh contains a mask for design sensitive bits in a compressed format. The Quartus® Prime software generates the sensitivity mask for the entire design. Hierarchy tagging provides the following benefits:
- Increases system stability by avoiding disruptive recovery procedures for inconsequential errors.
- Allows diverse corrective action for different design logic.