Advanced SEU Detection Intel® FPGA IP User Guide

ID 683542
Date 3/26/2019
Document Table of Contents

2.2. Off-Chip Lookup Sensitivity Processing

The Advanced SEU Detection IP core analyzes the content of the error detection block’s EMR and presents information to a system processor. The processor determines whether the failure affects the device operation. The system processor implements the algorithm to perform a lookup against the .smh.

The off-chip lookup sensitivity processing consists of two components:

  • Design logic to interpret content of the EMR of the CRC block and present the information to a processor interface.
  • Cache to store off-loaded content of the EMR.
Figure 3. System Overview for Off-Chip Lookup Sensitivity Processing

The EMR processing unit analyzes the content of EMR offloaded from the CRC block by the EMR Unloader IP core upon an SEU. The EMR processing unit writes each unique EMR value into cache, until the cache is full. When the cache is full, it asserts a cache overflow flag to the system interface.

For each new value written into cache, the EMR processing unit asserts an interrupt to the processor. The system processor reads the EMR value and performs a lookup against the .smh to determine the criticality of a CRAM location. After the system processor services the interrupt, the EMR processing unit advances the cache line and generates additional interrupt assertions, provided that there is an EMR value in cache that has not been processed.

After SMH lookup, the system processor determines the required corrective response.