Advanced SEU Detection Intel® FPGA IP User Guide

ID 683542
Date 3/26/2019
Public
Document Table of Contents

4.2.1. Using Partitions to Specify Logic Sensitivity ID

  1. In the Intel® Quartus® Prime software, designate a design block as a design partition.
  2. Specify the sensitivity ID assigned to the partition in the ASD Region column in the Design Partitions window.
    Figure 11. ASD Region Column in the Design Partitions Window
    Assign the partition a numeric sensitivity value from 0 to 16. The value represents the sensitivity tag associated with the partition.
    • A sensitivity tag of 1 is the same as no assignment, and indicates a basic sensitivity level, which is "region used in design". If a soft error occurs in this partition, the Advanced SEU Detection IP core reports the error as a critical error in the sensitivity region 1.
    • A sensitivity tag of 0 is reserved, and indicates unused CRAM bits. You can explicitly set a partition to 0 to indicate that the partition is not critical. This setting excludes the partition from sensitivity mapping.
Note: You can use the same sensitivity tag for multiple design partitions.

Alternatively, use the following assignment:

set_global_assignment -name PARTITION_ASD_REGION_ID <asd_id> -section_id <partition_name>