Advanced SEU Detection Intel® FPGA IP User Guide

ID 683542
Date 3/26/2019
Document Table of Contents

3.2. Advanced SEU Detection IP Core Parameters

Parameter Group Parameter Description
Name Legal Value
General CRC error cache depth 2, 4, 8,16, 32, 64
  • Specifies how many non-critical cyclic redundancy check (CRC) error to ignore.
  • Default value is 8.
Largest ASD region ID 1 to 16
  • Indicates the largest ASD SEU detection region ID in your design.
  • Configures the width of the regions_report port.
  • Default value is 1.
Sensitivity Data Access Use on-chip sensitivity processing ON, OFF
  • Configures the IP core to use on-chip sensitivity processing or off-chip sensitivity processing.
  • When enabled, implements an external memory interface in the IP.
Memory interface address width
  • Specifies width of the address bus connected to the external memory interface.
  • Default value is 32.

For on-chip sensitivity processing only.

Sensitivity data start address
  • Specifies the offset added to all addresses the external memory interface generates.
  • Default value is 0x0.

For on-chip sensitivity processing only.