Advanced SEU Detection Intel® FPGA IP User Guide

ID 683542
Date 3/26/2019
Document Table of Contents

2. Advanced SEU Detection Intel® FPGA IP Functional Description

The following Intel® FPGA devices contain a cyclic redundancy check (CRC) value per CRAM frame. The EDCRC logic can also determine the location and type of upset.

  • Intel® Arria® 10, Intel® Cyclone® 10 GX, Stratix® V, Arria® V, and Cyclone® V device families contain a 32 bit CRC value
  • Stratix® IV and Arria® II devices contain a 16 bit CRC value

The Intel® Quartus® Prime software can generate a Sensitivity Map Header File (.smh) of the configuration regions of your design that are sensitive to SEU. The software uses the design hierarchy and its assigned advanced SEU detection (ASD) region to to create the .smh. During sensitivity processing, the Advanced SEU Detection IP core uses the location information contained in the device EMR to look up the upset location in the .smh. It returns whether or not the bit is critical for the design.

You can instantiate the Advanced SEU Detection IP core with the following configurations:

  • On-Chip Lookup Sensitivity Processing—The sensitivity processing soft IP provides error location reporting and lookup.
  • Off-Chip Lookup Sensitivity Processing—An external unit (such as a microprocessor) performs error location lookup using the EMR information.