Advanced SEU Detection Intel® FPGA IP User Guide

ID 683542
Date 3/26/2019
Document Table of Contents

2.1. On-Chip Lookup Sensitivity Processing

All device families that support SEU detection include a hardened error detection block. This block detects soft errors and provides the location of single-bit errors and double-bit adjacent errors for supported devices. The Advanced SEU Detection IP core reads the error detection register of the error detection block, and then compares single-bit error locations with a sensitivity map. This check determines whether or not the failure affects the device operation.

Figure 1. System Overview for On-Chip Lookup Sensitivity Processing

The Advanced SEU Detection IP core accesses the EMR content (provided by the EMR Unloader IP core or user logic), analyzes the EMR content, and issues a query to an external memory containing the sensitivity map. The system designer must provide the information for the memory access logic and external memory.

To mitigate SEU in the error detection logic, implement an SEU detection circuit that tolerates a soft error in its logic. For example, instantiate two instances of the Advanced SEU Detection IP core in your design and then compare the output of the instances. Each instance of the IP core highlights errors that occur in the other instance as “critical.”