Advanced SEU Detection Intel® FPGA IP User Guide

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ID 683542
Date 11/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Advanced SEU Detection Intel® FPGA IP Overview 2. Advanced SEU Detection Intel® FPGA IP Functional Description 3. Using the Advanced SEU Detection Intel® FPGA IP 4. SEU Mitigation on CRAM Array 5. Advanced SEU Detection Intel® FPGA IP User Guide Archives 6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide
2. Advanced SEU Detection Intel® FPGA IP Functional Description x
2.1. On-Chip Lookup Sensitivity Processing 2.2. Off-Chip Lookup Sensitivity Processing
2.1. On-Chip Lookup Sensitivity Processing x
2.1.1. On-Chip Sensitivity Processor 2.1.2. On-Chip Processing Signals
2.2. Off-Chip Lookup Sensitivity Processing x
2.2.1. Off-Chip Lookup Sensitivity Processing Operation Flow 2.2.2. External Sensitivity Processor 2.2.3. Off-Chip Processing Signals 2.2.4. SMH Lookup
2.2.4. SMH Lookup x
2.2.4.1. SMH File Types
3. Using the Advanced SEU Detection Intel® FPGA IP x
3.1. Customizing and Generating IP Cores 3.2. Advanced SEU Detection IP Core Parameters
3.1. Customizing and Generating IP Cores x
3.1.1. IP Catalog and Parameter Editor 3.1.2. The Parameter Editor 3.1.3. Specifying IP Core Parameters and Options
3.1.3. Specifying IP Core Parameters and Options x
3.1.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
4. SEU Mitigation on CRAM Array x
4.1. Enabling the Advanced SEU Detection Feature in the Quartus® Prime Software 4.2. Hierarchy Tagging 4.3. Sensitivity Map Header File Lookup
4.2. Hierarchy Tagging x
4.2.1. Using Partitions to Specify Logic Sensitivity ID
4.3. Sensitivity Map Header File Lookup x
4.3.1. Programming Sensitivity Map Header File into Memory 4.3.2. Performing a Lookup for SMH Revision 1 ( Stratix® IV and Arria® II) 4.3.3. Performing a Lookup for SMH Revision 2 ( Stratix® V, Arria® V, and Cyclone® V Devices) 4.3.4. Performing a Lookup for SMH Revision 3 ( Arria® 10 and Cyclone® 10 GX Devices)
1. Advanced SEU Detection Intel® FPGA IP Overview
2. Advanced SEU Detection Intel® FPGA IP Functional Description
3. Using the Advanced SEU Detection Intel® FPGA IP
4. SEU Mitigation on CRAM Array
5. Advanced SEU Detection Intel® FPGA IP User Guide Archives
6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide

2.1.2. On-Chip Processing Signals

Figure 2.  Advanced SEU Detection IP Core Signals for On-Chip Processing
Table 2.   Advanced SEU Detection IP Core Signals for On-Chip Processing
Interface Signals Type Width Description
Clock and Reset clk Input 1
  • Clock input.
  • Use the same input clock as the EMR Unloader IP core. The input frequency must be sufficient to process the EMR content before the next content may become available. For example, a minimum recommended frequency for Stratix V devices is 30 MHz.

    If the frequency is too low, the IP core asserts the critical_error signal if new EMR content becomes available while the IP core is processing the current content.

reset Input 1 Active-high reset.
Cache Configuration cache_comparison_off Input 1
  • Static input signal.
  • Commands the IP core to bypass cache comparison. The EMR value is stored even if it already exists in the cache.
  • You can use this signal with the internal scrubbing feature for custom design.
Avalon Streaming (Avalon-ST) Sink Interface Signals1 emr Input
  • 46 (Stratix IV)
  • 67 ( Cyclone® V, Arria® V, and Stratix® V)
  • 119 ( Arria® 10 and Cyclone® 10 GX) 2
Error Message Register (EMR) data input from the EMR Unloader IP core.
emr_valid Input 1 Indicates when emr data input is valid.
emr_error Input 1
  • Indicates when emr data is ignored due to an error.
  • This error may occur when there is a data overrun from the Intel® Unloader IP core.
Errors noncritical_error Output 1 Indicates that an SMH lookup determined that the EDCRC error is in a non-critical region.
critical_error Output 1 Indicates that an SMH lookup determined that the EDCRC error is in a critical region.
regions_report Output 1
  • The advanced SEU detection (ASD) region for the error, as reported by the SMH lookup.
  • The Largest ASD region ID used parameter sets this port's width.
critical_clear Input 1
  • Optional input signal.
  • Assert this signal to clear error report for the last processed EMR data input.
  • Clears critical_error and regions_report, or noncritical_error.
busy Output 1
  • Optional output signal.
  • Logic high indicates that the ASD IP is busy processing EMR data input.
  • Signal goes low when processing completes and either the critical_error or noncritical_error signal is asserted.
External Memory Avalon Memory Mapped (Avalon-MM) Master mem_addr Output  
  • Output to the user logic.
  • Byte address of the 32 bit word to be read.
mem_rd Output  
  • Output to the user logic.
  • Signals to the user logic to request a read operation.
mem_bytesel Output  
  • Output to the user logic.
  • A 4 bit signal that selects the bytes needed by the IP core. This signal allows 16 bit or 8 bit memories to optimize the number of reads in cases where the IP does not need all 32 bits. If bit 0 of mem_bytesel is 0, the IP core ignores bits 0 to 7 of mem_data. Similarly, if bit 0 of mem_bytesel is 0, the IP core ignores bits 1 to 3.
mem_wait Input  
  • Input from the user logic.
  • Signals to the memory interface that the read operation is still running. Must be high by the first rising clock after mem_rd is asserted to hold the IP core in a wait state.
mem_data Input  
  • Input from the user logic.
  • 32 bit data bus. Data must be present if mem_wait goes high and if mem_rd returns low.
mem_datavalid Input  
  • Input from the user logic.
  • Signals that the mem_data signal contains valid data in response to a previous mem_rd request.
Related Information
1 Connect the Avalon-ST streaming sink interface to the corresponding Avalon-ST source interface of the EMR Unloader IP core.
2 The actual EMR data is 78 bits only, [77:0]. Bits [118:78] are reserved.
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