Integer Arithmetic Intel® FPGA IP Cores User Guide

ID 683490
Date 4/01/2024
Document Table of Contents

13.2. Verilog HDL Prototype

The following Verilog HDL prototype is located in the Verilog Design File (.v) altera_mf.v in the < Quartus® Prime installation directory>\eda\synthesis directory.

module altsqrt
# (parameter lpm_hint = "UNUSED",
parameter lpm_type = "altsqrt",
parameter pipeline = 0,
parameter q_port_width = 1,
parameter r_port_width = 1,
parameter width = 1)
(input wire aclr,
input wire clk,
input wire ena,
output wire [q_port_width-1:0] q,
input wire [width-1:0] radical,
output wire [r_port_width-1:0] remainder);