Integer Arithmetic Intel® FPGA IP Cores User Guide

ID 683490
Date 4/01/2024
Document Table of Contents

7.7. Encoder Ports

The following tables list the input and output ports for the ALTECC encoder IP core.

Table 22.  ALTECC Encoder Input Ports
Port Name Required Description
data[] Yes Data input port. The size of the input port depends on the WIDTH_DATAWORD parameter value. The data[] port contains the raw data to be encoded.
clock Yes Clock input port that provides the clock signal to synchronize the encoding operation. The clock port is required when the LPM_PIPELINE value is greater than 0.
clocken No Clock enable. If omitted, the default value is 1.
aclr No Asynchronous clear input. The active high aclr signal can be used at any time to asynchronously clear the registers.
Table 23.  ALTECC Encoder Output Ports
Port Name Required Description
q[] Yes Encoded data output port. The size of the output port depends on the WIDTH_CODEWORD parameter value.