Integer Arithmetic Intel® FPGA IP Cores User Guide

ID 683490
Date 4/01/2024
Document Table of Contents

13.5. Ports

The following tables list the input and output ports for the ALTSQRT IP core.
Table 56.  ALTSQRT Input Ports
Port Name Required Description
radical[] Yes Data input port. The size of the input port depends on the WIDTH parameter value.
ena No Active high clock enable input port.
clk No Clock input port that provides pipelined operation for the ALTSQRT IP core. For the values of PIPELINE parameter other than 0 (default value), the clock port must be connected.
aclr No Asynchronous clear input port. that can be used at any time to reset the pipeline to all 0s, asynchronously to the clock signal.
Table 57.  ALTSQRT Output Ports
Port Name Required Description
remainder[] Yes The square root of the radical. The size of the remainder[] port depends on the R_PORT_WIDTH parameter value.
q[] Yes Data output. The size of the q[] port depends on the Q_PORT_WIDTH parameter value.