Integer Arithmetic Intel® FPGA IP Cores User Guide

ID 683490
Date 4/01/2024
Document Table of Contents

5.1. Features

The LPM_ADD_SUB IP core offers the following features:

  • Generates adder, subtractor, and dynamically configurable adder/subtractor functions.
  • Supports data width of 1–256 bits.
  • Supports data representation format such as signed and unsigned.
  • Supports optional carry-in (borrow-out), asynchronous clear, and clock enable input ports.
  • Supports optional carry-out (borrow-in) and overflow output ports.
  • Assigns either one of the input data buses to a constant.
  • Supports pipelining with configurable output latency.