Integer Arithmetic Intel® FPGA IP Cores User Guide

ID 683490
Date 4/01/2024
Document Table of Contents

11.1. Features

The ALTMULT_ADD IP core offers the following features:

  • Generates a multiplier to perform multiplication operations of two complex numbers
  • Supports data widths of 1– 256 bits
  • Supports signed and unsigned data representation format
  • Supports pipelining with configurable output latency
  • Provides a choice of implementation in dedicated DSP block circuitry or logic elements (LEs)
    Note: When building multipliers larger than the natively supported size there may/will be a performance impact resulting from the cascading of the DSP blocks.
  • Provides an option to dynamically switch between signed and unsigned data support
  • Provides an option to dynamically switch between add and subtract operation
  • Provides an option to set up data shifting register chains
  • Supports hardware saturation and rounding (for selected device families only)
  • Supports optional asynchronous clear and clock enable input ports