Integer Arithmetic Intel® FPGA IP Cores User Guide

ID 683490
Date 4/01/2024
Document Table of Contents

12.4. Features

The ALTMULT_COMPLEX IP core offers the following features:

  • Generates a multiplier to perform multiplication operations of two complex numbers
    Note: When building multipliers larger than the natively supported size there may/will be a performance impact resulting from the cascading of the DSP blocks.
  • Supports data width of 1–256 bits
  • Supports signed and unsigned data representation format
  • Supports canonical and conventional implementation modes
  • Supports pipelining with configurable output latency
  • Supports optional asynchronous clear and clock enable input ports
  • Supports optional synchronous clear for Stratix® 10, Arria® 10, and Cyclone® 10 GX devices
  • Provides an option to dynamically switch between 36 × 36 normal mode and 18 × 18 complex mode (for Stratix V devices only)