Intel® Quartus® Prime Pro Edition User Guide: Getting Started

ID 683463
Date 3/28/2022

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2.6. Integrating Other EDA Tools

You can optionally integrate supported EDA synthesis, netlist partitioning, simulation, and signal integrity verification tools into the Intel® Quartus® Prime design flow.

The Intel® Quartus® Prime software supports input netlist files from supported EDA synthesis tools. The Compiler's EDA Netlist Writer module (quartus_eda) can automatically generate output files for processing in other EDA tools. The EDA Netlist Writer runs optionally as part of a full compilation, or you can run EDA Netlist Writer separately from the GUI or at the command line. The following functions are available to simplify EDA tool integration:

Table 4.  EDA Tool Integration Functions
EDA Integration Task EDA Integration Function
Specify settings for generation of output files for processing in other EDA tools. Click Assignments > Settings > EDA Tool Settings to specify options for supported tools.
Generate output files for processing in other EDA tools. Click Processing > Start > Start EDA Netlist Writer (or run quartus_eda) to generate files.

Compile RTL and gate-level simulation model libraries for your device, supported EDA simulators, and design language.

Click Tools > Launch Simulation Library Compiler to compile simulation libraries easily.
Generate EDA tool-specific setup scripts to compile, elaborate, and simulate Intel® FPGA IP models and simulation model library files. Specify options for Simulation file output when generating Intel® FPGA IP with IP parameter editor.
Generate files that allow supported EDA tools to perform netlist modifications, such as adding new modules, partitioning the netlist, and changing module connectivity. Use the quartus_eda –resynthesis command to generate a Verilog Quartus Mapping File (.vqm) that contains a node-level (or atom) representation of the netlist in standard structural Verilog RTL.

Include files generated by other EDA design entry or synthesis tools in your project as synthesized design files.

Click Project > Add/Remove Files In Project to add supported Design File files from other EDA tools.

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