Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 3/28/2022
Public

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5.4. Upgrade Non-Compliant Design RTL

The Intel® Quartus® Prime Pro Edition software introduces a new synthesis engine (quartus_syn executable).

The quartus_syn synthesis enforces stricter industry-standard HDL structures and supports the following enhancements in this release:

  • Support for modules with SystemVerilog Interfaces
  • Improved support for VHDL2008
  • New RAM inference engine infers RAMs from GENERATE statements or array of integers
  • Stricter syntax/semantics check for improved compatibility with other EDA tools

Account for these synthesis differences in existing RTL code by ensuring that your design uses standards-compliant VHDL, Verilog HDL, or SystemVerilog. The Compiler generates errors when processing non-compliant RTL. Use the guidelines in this section to modify existing RTL for compatibility with the Intel® Quartus® Prime Pro Edition synthesis.

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